SRAM Memory Testing Methods and Analysis: An Approach for Traditional Test Algorithms to ML Models

1. Introduction

Generally, IC testing comprises two ways: one is at the wafer level, and the other is at the package level. The wafer level test is a die or probe test that involves measurement of resistance and capacitance at the test location. If the observations differ from what was expected, this leads to fault identification. Similarly, the final test, which is the wafer test, will be done after packaging. This requires a probe, probe card, and test socket as a setup that decides whether the packaged chip has any faults or not. Deploying AI and machine learning (ML) algorithmic techniques in the VLSI domain at the design and manufacturing levels will reduce the test time. Most importantly, using automated learning algorithms will result in less effort in understanding and processing data at various abstraction levels. As a result, it reduces the manufacturing turnaround time, cost and further leads to an improvement in the IC yield. In general, defects in the IC layout will cause an effective fault in the circuit at the functional level. Machine learning helps while working with EDA tools in obtaining fault-free VLSI designs by predicting the defects on the chip and using that result to find better solutions during production.