Macro and Micro Architectures for Network on Chip: A Review

Introduction

As the number of Processing Elements (PEs) in Systems-on-Chip (SoCs) increases, traditional on-chip communication architectures may prevent these systems to meet the required performance of many applications. For a SoC with multiple processors (Multiprocessor SoC - MPSoC), different on-chip communication architectures have been proposed to meet such requirements like high performance, flexibility, scalability, reliability, efficiency and so on. Rather than using a traditional on-chip communication architectures such as bus communication architectures, point-to-point communication architecture and crossbar architectures, other communication architectures have also been proposed to meet the on-chip communication requirements (Pasricha & Dutt, 2008). Figure 1 shows the different on-chip communication architectures for SoC or MPSoC. Figure 1 (a) shows the traditional bus based communication architecture for MPSoC. The main challenge using bus communication architecture is the bottleneck due to the bandwidth limitation (Pasricha & Dutt, 2008), (Dally & Towles, 2004). Figure 1 (b) depicts the fully crossbar communication architecture for MPSoC but it leads to higher electromagnetic interference and parasitic capacitance problems due to the metal interconnections. The dedicated point-to-point communication architecture used for MPSoCs is shown in Figure 1 (c), but the limitation is flexibility.

Figure 1 (d) shows the segmented bus based communication architecture for MPSoC, in which a bus communication system is interconnected with the other bus communication system using bridge. This type of bus communication system helps to overcome the bandwidth limitation of traditional bus communication architecture, but it leads to complex design and more timing consumption. However, since distributed bus arbitration corresponds to the cumulative actions of multiple arbitration units, computing optimal overall settings will be very complex and time consuming (Dally & Towles, 2004). The NoC is the promising solution for such problems and requirements with irregular and regular structures as shown in Figure 1 (e) and Figure 1 (f). The NoC consists of several routers used to route a packet sent by one PE to another. Therefore, the main attitude of the NoC is the development of communication architecture that enables to route the packets instead of the wires. The use of NoCs can be classified into two main categories, i.e. in embedded SoC applications domain commonly called MPSoC and in general-purpose microcomputer systems domain commonly called Chip-Level Multiprocessor (CMP) systems (Benini & Micheli, 2002).

Figure 1.

Various communication architectures for MPSoCs: (a) Bus (b) Fully crossbar (c) Dedicated point to point (d) Segmented bus (e) Irregular network architecture (f) Regular network architecture

The PEs in the MPSoC send and receive messages to and from other PEs for interacting computational processes in order to complete parallel tasks in the embedded applications. The main aspect that should be taken into account in the MPSoC systems is the low power design. The power supply in the embedded applications, which is commonly used in electronic-handheld and portable electronic appliances, is limited by the battery life. Addition to the power constraint, logic area constraint is also the main issue in the design of the NoC-based MPSoC systems, because both are directly related to each other. Each PE is connected to one mesh router via an On-Chip Network Interface (OCNI). The OCNI is the main component used to assemble a data into a packet before the data is sent from one core to another core through the network node, which is then disassembled back to the original data before being sent to the core. The routing path can be determined by the routing algorithms based on the communication scheme, whether it is unicast communication method or multicast communication method. Therefore, the design concepts of NoC for MPSoCs involve the topology architectures, router architectures, routing algorithms with switching methods and OCNI design. Before entering to the literature survey, this chapter gives an overview of NoC concepts.