Low-Power Methodologies and Strategies in VLSI Circuits

Introduction

Since the transistor era, which laid the groundwork for low-power consuming gadgets, the microelectronics industry has experienced a significant boom. The electronic components (IC) reduced size while also enhancing the circuits' performance. This causes the area of the power in the components to increase. There is a great demand for low power consuming gadgets is driven by a striking increase in battery oriented complicated life rescuing devices. Nowadays more concentration is to develop low power devices and design methodologies. On the other hand, with high power consumption devices, the silicon failure rate doubles for every 10-degree increase in temperature. As deep submicron nodes and nanoscale technologies advanced, the unprecedented development of power reduction gained significance.

Very-Large-Scale Integration is a technique that builds an integrated circuit (IC) by fusing thousands of transistors with other devices onto a single chip. Today, designing low power consumption is the top priorities for intricate very large-scale integration (VLSI) circuits. Table 1.1 lists various VLSI technology and its representation. Evolution of IC Technology précised in Table 1.2.

Rapid and creative advancements in low-power design have occurred recently rising the popularity of mobile devices. Hence, there is a necessity to reduce power consumption in very-high density chips. The motivations for these advances include portable applications such laptops, portable devices, and personal digital assistants that require low power consumption and high throughput. In these situations, it is necessary to achieve both the challenging objectives of high chip density and throughput in addition to the low power consumption requirements. As a result, the field of CMOS design for low-power digital integrated circuits has become quite active and is expanding very quickly.

Low-power consumption in digital systems, achieved using a variety of approaches, ranging from device to algorithm level. Reduced power consumption is mostly a result of device parameters (such as threshold voltage), device geometries, and connection qualities. To reduce power dissipation at the transistor level, circuit-level techniques can be utilized. Circuit-level includes the selection of circuit design styles appropriately, lowering the voltage change, and clocking methods. Smart management of power technique of different blocks, the use of pipelining, parallelism, and the bus structure are examples of architecture-level controls. Finally, system power consumption can be reduced by carefully choosing the data processing algorithms and limiting the amount of switching events for a given activity.