Interrupts and Applications

Interrupt Mechanism

To facilitate the understanding of interrupts, we propose some real-life analogies. Suppose you are expecting someone to pay you a short visit. Imagine how inefficient it would be if you were to wait for your guest to show up on your front door while doing nothing. In order not to waste valuable time, you decide in the process to read an interesting book. When your guest appears at the front door of your house, he/she would ring the bell to indicate arrival. This bell ringing act signals an event: the arrival of your guest. Normally, you would respond right after you finish reading the current sentence. When you open the door and host your guest, your reading is interrupted. After servicing your guest by responding to his/her requests, you resume your reading at the point you left off. Normally, you would use a book marker to tell you where to continue.

At the microcontroller level, a similar process occurs. The CPU is normally busy running a certain task. The event that can interrupt it may occur periodically or intermittently. For example, if the MCU were to output a 1 KHz square wave, it would have to toggle a microcontroller pin, say RB0, every 500 μs. Timer0 which is an 8/16-bit counter may be programmed to generate a periodic interrupt every 500 μs. This interrupt event is indicated by setting a flag, namely TMR0IF. When the CPU responds to it and toggles RB0, an interrupt takes place. The CPU has the option to respond to an event by executing the corresponding ISR (interrupt-driven approach) or simply ignore it.

The first condition that must be satisfied in order for an interrupt to take place is the emergence of an event (external or internal). The hardware indicates the event to the CPU by setting a flip-flop or flag. For example, when Timer0 rolls over to a count of zero, flag TMR0IF (Timer0 interrupt flag) is set. All event indicating flags are “sticky” bits and hence they must be cleared within the interrupt service routine.

The occurrence of an event does not necessarily trigger an interrupt. There are two barriers that must be surmounted. These barriers are called interrupt masks and may be either global or local. A global mask acts very much like a university main gate. If it is open, everybody can get into the university. A local mask behaves much like the front gate of a faculty building. So in essence, a device requesting interrupt must have its local mask enabled in addition to the global mask. A programmer may wish to disable all interrupts by simply clearing the global mask.

As far as the global mask is concerned, there are actually two of them: the global interrupt enable bit (GIE) and the peripheral interrupt enable bit (PEIE). GIE enables the traditional interrupt sources similar to those of the older PIC16F84 microcontroller. The added interrupt sources pertaining to peripheral devices are enabled by asserting both GIE and PEIE. Table 1 lists the 33 interrupt sources along with their event indicator flags and local/global masks bits. Figure 2 shows the control register INTCON (Interrupt configuration register) pertaining to the following interrupt sources:

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  Detection of a rising or falling edge on INT0.

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  Detection of a level change on RB7... RB4.

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  Roll over of Timer0 from 0xFF (8-bit mode) or 0xFFFF (16-bit mode) to zero.