MLA
Niranjan, Vandana. "Dynamic Body Bias: A Transistor-Level Technique for the Design of Low-Voltage CMOS Analog Circuits." Energy Systems Design for Low-Power Computing, edited by Rathishchandra Ramachandra Gatti, et al., IGI Global, 2023, pp. 44-66. https://doi.org/10.4018/978-1-6684-4974-5.ch004
APA
Niranjan, V. (2023). Dynamic Body Bias: A Transistor-Level Technique for the Design of Low-Voltage CMOS Analog Circuits. In R. Gatti, C. Singh, S. P., & S. Bhat (Eds.), Energy Systems Design for Low-Power Computing (pp. 44-66). IGI Global. https://doi.org/10.4018/978-1-6684-4974-5.ch004
Chicago
Niranjan, Vandana. "Dynamic Body Bias: A Transistor-Level Technique for the Design of Low-Voltage CMOS Analog Circuits." In Energy Systems Design for Low-Power Computing, edited by Rathishchandra Ramachandra Gatti, et al., 44-66. Hershey, PA: IGI Global, 2023. https://doi.org/10.4018/978-1-6684-4974-5.ch004
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