Design of a New Single Phase 7-Level Reduced Switches Count Multilevel Inverter Topology

Design of a New Single Phase 7-Level Reduced Switches Count Multilevel Inverter Topology

Nikhil Agrawal, Dev Prakash Chourasia, Bharat Bhushan Khare
Copyright: © 2021 |Pages: 11
DOI: 10.4018/978-1-7998-7611-3.ch014
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Abstract

This chapter presents a new single-phase multilevel inverter topology. This topology requires fewer components in comparison to conventional multilevel inverter topology such as diode clamped, flying capacitor, and cascade h-bridge inverter. In this topology, no extra clamping diode and no extra clamping capacitor are required for operation. This chapter also presents the control and modulation techniques. These techniques applied on this proposed MLI topology and simulation result are calculated with the help of MATLAB/SIMULINK software and are compared on the basis of THD with over and under modulation index.
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2. Proposed Topology

Proposed topology structure is shown in the figure. The proposed topology have simple configuration of eight switch and three voltage source (Thiyagarajan et al., 2019). Here voltage source have same dc link voltage so proposed topology is the symmetrical MLI topology. The maximum voltage generated across the load is three times the magnitude of voltage source. This is the extendable topology. With this topology we can obtain higher level output just adding the switches to main configuration part. In this topology the witch is IGBT. The switching scheme is shown in table 1. At any level only four switch is ON at a time for voltage level generation.

Figure 1.

Circuit Diagram Proposed Topology

978-1-7998-7611-3.ch014.f01
Table 1.
Switching Configuration of Proposed Topology
Output Voltage LevelSwitches
S1S2S3S4S5S6S7S8
+3VdcONOFFONOFFOFFONOFFON
+2VdcONOFFONONOFFONOFFOFF
+VdcONOFFOFFOFFOFFONONON
0ONOFFOFFONOFFONONOFF
-VdcOFFONONONONOFFOFFOFF
-2VdcOFFONOFFOFFONOFFONON
-3VdcOFFONOFFONONOFFONOFF

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