Article Preview
TopIntroduction
The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years, and thus are utilizing more energy. These devices contain high-speed multi-core processors connected to large capacity dynamic random-access memory (DRAM) of as much as a few GB with large bandwidth. However, typical mobile devices are equipped with Li-ion batteries, which face a major issue related to power consumption and energy efficiency. Since the battery capacity of such a device is limited, operation must continue as long as possible with low power consumption. In contrast, applications running on mobile devices require higher performance every year, with high-performance computing resources required instantaneously. Because of the characteristics of such devices, high-speed processors and large-capacity memory are often necessary in some situations. In other situations, large resources are not necessary, but energy efficiency is. Thus, different situations with conflicting requirements can simultaneously arise on the same device.
One technique to resolve this situation in recent mobile devices is to use heterogeneous multicore central processing units (CPUs) (Kumar, Farkas, Jouppi, Ranganathan, & Tullsen, 2003). Such CPUs achieve improvement in power efficiency through dynamic management of computing power. Both high-performance and power-efficient cores can coexist to provide computing performance scalability. Thus, it is possible to turn off the CPU core when not required. When not running a task, the high-performance core can be shut down, with only the energy-efficient core operating. Thus, in recent mobile devices, scalability of computing power enhances power efficiency (Kumar, Tullsen, Ranganathan, Jouppi, & Farkas, 2004).
Although mobile devices are expected to have even greater power efficiency currently, it is difficult for the existing memory management scheme to efficiently handle the power management of DRAM (Wu, He, Tang, Xu, & Guo, 2012). DRAM, typically used in main memory, loses its storage contents when turned off. Hence, power cannot be cut off during device operation when DRAM is used as main memory. Recent smartphones and tablets have large capacity and high-speed DRAM. DRAM power consumption cannot be ignored in those devices. Moreover, DRAM consumes power even in the stand-by mode, when there is no memory access.
To solve this problem, we focus on the emerging technology of non-volatile memory (NVM), which has attracted attention in recent years. NVM is a new memory technology that includes spin-transfer torque magnetic RAM (STT-MRAM), phase-change memory (PCM), and resistive RAM (ReRAM). These memory devices, also called persistent memory, are currently in the productization or research and development stage for some vendors. NVM is expected to become popular in the near future. These devices are non-volatile in that the contents of the data are not lost even when the power is turned off. Emerging NVM devices have common characteristics with DRAM (Smith, Wang, & Fujino, 2013). The access latency and read/write performance are comparable with those of DRAM. NVM is expected to be able to achieve a potentially large capacity. Moreover, it has byte-addressable storage, unlike recent NAND flash storage, such as solid-state drives (SSD). NAND flash storage, which revolutionized computer storage by replacing hard disks, is a block device that can be accessed only in block units. Since a byte is addressable, it can be used in almost the same manner as DRAM (Eilert, Leinwander, & Crisenza, 2009). Some devices have limited write endurance, similar to NAND flash memory, and it is necessary to level wear properly. However, they have longer life expectancy than NAND flash and a shorter writing lifetime than STT-MRAM (Wang, Alzate, & Amiri, 2013). With these characteristics, the emerging NVM has the potential to be used as main memory, similar to DRAM (Kang, 2014). Furthermore, it can retain contents while the power is off.