Article Preview
TopIntroduction
The performance after fabrication of analog and mixed integrated circuits is less predictable for present and future technologies than it was in the past. Because of that, design techniques tolerant to process variations are topics of active research.
Reconfiguration techniques can be used to design circuits tolerant to process variations and circuits capable of changing their specifications. This work addresses the former. Here, reconfiguration is defined as the capability of some circuit blocks to change their default connections with other blocks, as well as their operation. By changing their default connections, damaged blocks could be bypassed, for example, if some degree of redundancy is present in the circuit, leading to an increase of the yield of these circuits. By changing their operation, the performance of the blocks can be measured (Hong, Liang, & Song, 2009).
Reconfiguration techniques seem well-suited to pipelined analog-to-digital converters (ADCs), because they fulfill two conditions. First, pipelined ADCs can be designed as a set of functionally identical stages, each processing part of the digital output signal as an analog residue goes through the front-end stages to the back-end ones. Second, the contribution to the overall ADC error of each stage depends on its position in the ADC, being the front-end stage errors those contributing the most.
The ADC reconfiguration method proposed in this work sets the best MDAC, in terms of the actual bandwidth after manufacturing, at the logical front-end of the analog residue processing chain, no matter what their physical position is, to reduce nonlinear errors due to finite bandwidth. The best MDAC is chosen from a set of nominally identical stages by means of an alternate-test based technique (Arabi & Kaminska, 2007; Srinivasan, Goyal, & Chatterjee, 2004). Then, each one of these stages can be reconfigured (including MDAC interconnections and scaling) according to its given logical positions. These logical positions should be set as quickly as possible by cheap means. This can be accomplished by the alternate test methodology included in this work to lead the pipelined ADC reconfiguration. In fact, this method implies another reconfiguration: during circuit start-up, the stages are sequentially reconfigured as oscillators and their oscillation frequencies are compared. Such a comparison allows for a fast and precise sorting of the stages depending on their frequency response. Thus, the logical position of the stages in the ADC can be changed according to this information to reduce bandwidth-related errors. This method can be implemented as a built-in self-test (BIST), i.e., the whole technique can be implemented with no need of external automated test equipment (ATE).
A similar reconfigurable pipelined ADC has been previously reported in the literature (Liu & Hassoun, 2002). In that work, the configuration to be used in normal operation is chosen from a large collection of possible configurations, to improve the effective number of bits (ENOB) after manufacturing. The best configuration is determined by performing exhaustive measurements of the ENOB by means of ATE. This is a slow and expensive method. The designs of other previously reported reconfigurable pipelined ADCs are oriented to change their specifications as wished inside a given range (Anderson, Norling, Dreyfert, & Yuan, 2005).
The main errors present in pipelined ADCs are comparator offsets, process variations on interstage gains, and bandwidth- and slew-rate-related errors. Comparator offset errors can be corrected after applying redundancy by digital correction and other error correction techniques. For low- and medium-resolution ADCs (less than 10 bits), process variations on interstage gain errors are not a limiting factor provided that high-gain operational amplifiers (op amps) are used (Murmann, 2008; Sedighi & Bakhtiar, 2009). For high-resolution ADCs or low-gain op amps, some kind of calibration is needed (Chang, Ahn, & Moon, 2005; Grace, Hurst, & Lewis, 2005). For high-speed ADCs (more than 50 MHz), the main remaining sources of nonlinear errors are induced by the finite bandwidth and the slew-rate of the op amps embedded in each pipelined stage. This work addresses the bandwidth-related errors for low- and medium-resolution, high-speed ADCs.