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Top1. Introduction
Single-chip multicore processors and their network on chip (NoC) interconnection mechanisms have received extensive interest since the early 2000s. They have become attractive as the number of transistors that can be placed on a single die has continued to increase, as per Moore’s law. A multicore processor consists of multiple processing cores that can execute instructions in parallel. Multicore processors that consist of a large number (tens to thousands) of relatively simple cores are referred to as manycore processors. Manycore processors have for goal achieving a high level of explicit parallelism.
The mesh interconnection topology is popular in NoCs. This includes both 2D and 3D meshes (Matsutani et al., 2007; Wentzlaff et al., 2007). An example is the 2D 8×10 mesh interconnection network used in an Intel manycore research chip that integrates 80 cores. Each of the cores contains a processing element (PE) and a 5-port router for communication (Vangal et al., 2007). Four ports are used for communicating with the east, west, north, and south neighbors of internal PEs or cores, as in Figure 1. Edge and corner cores have fewer neighbors. The fifth port is for communication with the PE. Another example is the TRIPS On-Chip Network (OCN) that uses a 4x10 wormhole-routed 2D mesh interconnection network (Gratz et al., 2007). A 1024-node manycore system that has a mesh topology, and is partitioned into 32 clusters, where each cluster is 4×8 mesh, has been proposed recently. To decrease the system’s overall diameter, each cluster has in its middle a Radio Hub (RH) that attaches to the four routers of the middle cluster node. Communications between clusters takes place through the Radio Frequency (RF) waveguides of the RHs. Within clusters, communication takes place over a mesh interconnection network (Lahdhiri et al., 2020).
A 2D mesh interconnection network (see Figure 1) is an example of direct networks, in which each processer or core is connected directly to its neighbors. In addition to being used over the past two decades in multicore systems, the 2D mesh interconnection network had been used in earlier large-scale multicomputer systems. This is due to its simplicity, regularity, scalability (i.e., it can be scaled up as the system needs), as well as its ease of implementation, and ability to benefit from the locality property in communication for many parallel applications. The 3D mesh is an extension of the 2D system, where several 2D mesh chips are stacked vertically on top of each other with additional top and down interconnection links, as appropriate.
A common issue in mesh NoCs is that they can suffer from high energy consumption and temperatures. Mapping communicating tasks to neighboring cores can reduce communication delays and associated power consumption and improve throughput and job execution times (Mosayyebzadeh et al., 2016; Agyeman et al., 2018; Dahir et al., 2021).